I’m Yun-Sheng Chang, a research assistant at Academia Sinica, Taiwan, working with Dr. Yu-Fang Chen and Dr. Hsiang-Shang Ko. My current research focuses on building an efficient yet verifiable storage stack.
I graduated in 2019 from National Tsing Hua University, where I got my B.S. and M.S. degrees in Electrical Engineering, advised by Prof. Ren-Shuo Liu.
Determinizing Crash Behavior with a Verified Snapshot-Consistent Flash Translation Layer.
Yun-Sheng Chang, Yao Hsiao, Tzu-Chi Lin, Che-Wei Tsao, Chun-Feng Wu, Yuan-Hao Chang, Hsiang-Shang Ko, and Yu-Fang Chen.
USENIX Symposium on Operating Systems Design and Implementation (OSDI), Virtual Event, November 4–6, 2020.
Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN).
Yun-Chen Lo, Yu-Chun Kuo, Yun-Sheng Chang, Jian-Hao Huang, Jun-Shen Wu, Wen-Chien Ting, Tai-Hsing Wen, and Ren-Shuo Liu.
European Solid State Circuits Conference (ESSCIRC), Krakow, Poland, September 23-26, 2019.
OPTR: Order-Preserving Translation and Recovery Methods for SSDs with a Standard Block Device Interface.
Yun-Sheng Chang and Ren-Shuo Liu.
USENIX Annual Technical Conference (USENIX ATC), Renton, USA, July 10–12, 2019.
A 65nm 1Mb Nonvolatile Computing-in-Memory ReRAM Macro with Sub-16ns Multiply-and-Accumulate for Binary DNN AI Edge Processors.
Wei-Hao Chen, Kai-Xiang Li, Wei-Yu Lin, Kuo-Hsiang Hsu, Pin-Yi Li, Cheng-Han Yang, Cheng-Xin Xue, En-Yu Yang, Yen-Kai Chen, Yun-Sheng Chang, Tzu-Hsiang Hsu, Ya-Chin King, Chorng-Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, and Meng-Fan Chang.
International Solid-State Circuits Conference (ISSCC), San Francisco, USA, February 11-15, 2018
VST: A Virtual Stress Testing Framework for Discovering Bugs in SSD Flash-Translation Layers.
Ren-Shuo Liu, Yun-Sheng Chang, and Chih-Wen Hung.
International Conference on Computer Aided Design (ICCAD), Irvine, USA, November 13-16, 2017.